1. Field of the Invention
The present invention relates to a voltage generating apparatus, and more particularly to a D/A converter, a method of designing a D/A converter, a method of precharging signal lines, a circuit for precharging signal lines, and a liquid crystal panel substrate and liquid crystal display device using the above component(s) and method(s).
2. Background of the Invention
A great number of techniques have been developed to generate a voltage in response to a given signal. However, the problems of these known techniques are that the voltage can deviate from a desired value and that a long time is required for the voltage to reach the final desired value. These problems will be discussed in further detail below.
(1) Deviation of Voltage
One known technique of constructing a D/A converter is to use capacitors. The advantage of the D/A converter using capacitors over the D/A converter with resistors is its low power consumption. One type of the D/A converter using capacitors is one with capacitors having capacitance values weighted in a binary fashion. FIG. 74 is a circuit diagram illustrating a conventional D/A converter with binary-weighted capacitors.
This D/A converter shown in FIG. 74 generates an analog output signal corresponding to a 6-bit digital input signal. More specifically, a 6-bit digital signal representing a binary number in the range from "000000" to "111111" (from "0" to "63" in decimal) is input wherein the 6 bits D11-D16 corresponding to the first to sixth digits of the binary number respectively are input via six digital signal lines 5001.
The respective bits D11-D16 of the input digital signal are stored in 2-stage latches A11-A16 and B11-B16. The latches A11-A16 and B11-B16 operate in response to clock signals CL1 and CL2 and also to inverted clock signals nCL1 and nCL2. These clock signals CL1 and CL2 and inverted clock signals nCL1 and nCL2 are generated from the output signal of a shift register (not shown).
The D/A converter has an interconnection line 5002 (at a voltage Vo), interconnection line 5003 (at a voltage Vs), interconnection line 5004 (at ground voltage GND), wherein Vo&gt;Vs&gt;GND. The D/A converter also has an interconnection line 5005 for outputting the analog output signal.
One electrode of each conversion capacitor C11-C16 is connected to the interconnection line 5002. The conversion capacitors C11-C16 are designed to have binary-weighted capacitance values. That is, the ratios of the capacitance values are given by:
C11: C12: C13: C14: C15: C16=1: 2: 4: 8: 16: 32. PA1 Ci: ith conversion capacitance, PA1 Coi: designed value of the ith conversion capacitance, PA1 dCi: dispersion of the ith conversion capacitance, PA1 Cj: jth conversion capacitance, PA1 Coj: designed value of the jth conversion capacitance, PA1 dCj: dispersion of the jth conversion capacitance, PA1 .SIGMA..sub.(i&lt;j) : sum for all i smaller than j, and PA1 for all j: indicating that the equation should be satisfied for all j. PA1 the conversion capacitors may be made up of an insulating film and two electrodes formed of either a thin amorphous film or a thin polysilicon film, the insulating film being disposed between the two electrodes; and PA1 the thin film transistors (TFTs) forming the analog switches and the conversion capacitors may be formed on the same substrate. PA1 Coi and dCi are set for all i; PA1 j is set such that j=2; PA1 it is checked whether equation (1) described above is satisfied or not, and if it is concluded that equation (1) is not satisfied, the value of Coj is modified; PA1 j is incremented; and PA1 steps 3 and 4 are performed repeatedly for all j. PA1 Cs: coupling capacitance, PA1 Vc: voltage at the other end of the coupling capacitor before the switch is closed, PA1 Vo: voltage at the other end of the conversion capacitors before the switch is closed, PA1 Coi: designed value of the ith conversion capacitance, PA1 dCi: dispersion of the ith conversion capacitance, PA1 Coj: designed value of the jth conversion capacitance, PA1 dCj: dispersion of the jth conversion capacitance, PA1 Vth: maximum change (visually recognizable threshold value) in the output voltage of the D/A converter, which cannot be recognized by human eyes when an image is displayed in such a manner that the brightness of the image corresponds to the output voltage of the D/A converter, PA1 .SIGMA..sub.(i&lt;j) : sum for all i smaller than j, and PA1 for all j: indicating that the equation should be satisfied for all j. PA1 Coi and dCi are set for all i; PA1 j is set such that j=2; PA1 it is checked whether equation (2) described above is satisfied or not, and if it is concluded that equation (2) is not satisfied, the value of Coj is modified; PA1 j is incremented; and PA1 steps 3 and 4 are performed repeatedly for all j. PA1 the liquid crystal panel substrate being characterized in that the driving circuit for driving the plurality of signal lines includes the D/A converter described above. PA1 n conversion capacitors Cxi corresponding to the respective bits Di of the digital signal; PA1 at least one conversion selection line along which n different voltages Vxi corresponding to the respective bits Di of the digital signal; PA1 an output line via which the analog output signal Vout is output; and PA1 a first reference voltage line connected to one electrode of each conversion capacitor Cxi and maintained at a voltage Vs1; PA1 wherein the other side electrodes of those of the conversion capacitors Cxi corresponding to those of the bits Di of the digital signal in an on-state are connected to the conversion selection line so that conversion charges corresponding to the differences between the voltages Vxi and Vs1 are stored in the corresponding conversion capacitors Cxi; PA1 the other side electrodes of those of the conversion capacitors Cxi corresponding to those of the bits Di of the digital signal in an off-state are connected to a predetermined line; PA1 after the conversion charges have been stored, the other side electrodes are electrically disconnected from the conversion selection line or the predetermined line and then connected to the output line so that the conversion charges are all combined together and an analog output signal Vout corresponding to the total charge is output. PA1 a second reference voltage line maintained at a voltage Vs2; and PA1 a reference capacitor Cs formed on the output line, for storing a reference charge corresponding to the difference between the voltages Vs1 and Vs2 on the first and second reference voltage lines; PA1 wherein the predetermined line, to which the other side electrodes of those of the conversion capacitors Cxi corresponding to those of the bits Di of the digital signal in the off-state are connected, constitute the first reference voltage line; PA1 the total charge is the sum of the conversion charges and the reference charge; and PA1 the analog output signal Vout is given by EQU Vout=(.SIGMA.Cxi(Di.multidot.Vxi+Vs1(1-Di))+Cs.multidot.Vs2)/ (.SIGMA.Cxi+Cs) PA1 a first switch connected between the other side electrodes of the conversion capacitors Cxi and the conversion selection line; PA1 a second switch connected between the other side electrodes of the conversion capacitors Cxi and the predetermined line; and PA1 a third switch connected between the other side electrodes of the conversion capacitors Cxi and the output line. PA1 first switch connected between the other side electrodes of the conversion capacitors Cxi and the conversion selection line; PA1 a second switch connected between the other side electrodes of the conversion capacitors Cxi and the first reference voltage line; PA1 a third switch connected between the other side electrodes of the conversion capacitors Cxi and the output line; and PA1 a fourth switch for controlling electric connection so that an voltage is applied to the reference capacitor Cs from either the first or second reference voltage line. PA1 a high voltage line, a low voltage line, and n-1 resistors connected in series between the high voltage line and the low voltage line; PA1 wherein the conversion selection lines comprise: a line connecting a resistor directly to the high voltage line; lines connecting adjacent resistors; and a line connecting a resistor directly to the low voltage line. PA1 it is preferable that there be provided one conversion selection line, the voltage supplied on which varies with time so that n different voltages Vxi are supplied. PA1 n conversion pulse lines corresponding to the respective n conversion capacitors Cxi; PA1 wherein whenever the time-varying voltage on the conversion selection line reaches a voltage Vxi to be supplied to a corresponding conversion capacitor Cxi, a pulse signal is applied to a corresponding one of the conversion pulse lines; and PA1 in response to the pulse signal, the voltage Vxi is supplied to the conversion capacitor Cxi. PA1 it is preferable that the n different voltages Vxi supplied to the conversion selection lines form a geometric progression with a common ratio of 2. PA1 n conversion capacitors Cxi corresponding to the respective bits Di of the digital signal; PA1 at least one conversion selection line via which different voltages Vxi are supplied; PA1 wherein the voltages Vxi and the capacitance values of the conversion capacitors Cxi are set so that conversion charges corresponding to the respective bit values Di of the digital signal are stored in the corresponding conversion capacitors Cxi and so that an analog output signal Vout corresponding to the total value or the sum of the conversion charges is output. PA1 for each on-state bit of the digital signal, storing a conversion charge into the corresponding one of n conversion capacitors Cxi in accordance with the corresponding voltage of n different voltages Vi, while maintaining the conversion charges, stored in those of the conversion capacitors Cxi corresponding to the off-state bits Di of the digital signal, constant regardless of the bits Di; and PA1 determining the sum of the conversion charges and supplying an analog output signal Vout corresponding to the total charge equal to the sum of the conversion charges. PA1 it is preferable that if the capacitance values of the conversion capacitors Cxi are different from their designed values, the voltages Vi are adjusted so that the corresponding conversion charges become substantially equal to their designed values. For example, when the actual capacitance values of the conversion capacitors Cxi' are different from their designed values Cxi0, if the mean value of the actual capacitances is equal to the designed value, the voltages Vxi' are adjusted such that EQU Vxi'=(Cxi0/Cxi').times.Vxi0. PA1 it is also preferable that a reference charge be stored in a reference capacitor so that a corresponding increase occurs in the analog output signal Vout regardless of the on/off state of the digital signal Di; PA1 and that the total charge be the sum of the conversion charges and the reference charge. PA1 for each on-state bit Di of the digital signal, selecting one voltage from a plurality of different voltages Vxi in accordance with each on-state bit Di of the digital signal, and storing a corresponding conversion charge into the corresponding one of the n conversion capacitors Cxi, while maintaining the conversion charges, stored in those of the conversion capacitors Cxi corresponding to the off-state bits Di of the digital signal, constant regardless of the bits Di; and PA1 determining the sum of the conversion charges and supplying an analog output signal Vout corresponding to the total charge equal to the sum of the conversion charges. PA1 a driving circuit for driving the liquid crystal panel; a pixel electrode for applying a voltage to a liquid crystal; and a thin film transistor for controlling the supply of the voltage to the pixel electrode; wherein the driving circuit includes the D/A converter described above. PA1 one horizontal scanning period comprises a scanning signal selection period and a blanking period disposed between the selection period and the following selection period; and PA1 the storage of the total charge and the supply of the analog output signal Vout are performed during the blanking period. PA1 one horizontal scanning period comprises a scanning signal selection period and a blanking period disposed between the selection period and the following selection period; PA1 the storage of the total charge is started in the blanking period; and PA1 in the following horizontal scanning period, the storage of the total charge is completed and the analog output signal Vout is supplied. PA1 preparing switches such that each signal line has its own one switch serving to select one of different precharging DC voltages and selectively connect the signal line to the selected precharging DC voltage; and PA1 operating the switches so that the signal lines are connected to one of the precharging DC voltages, thereby precharging the signal line into the same polarity as the polarity of the image signal relative to the center voltage of its amplitude. PA1 preparing a first precharging voltage line, a second precharging voltage line having a voltage different from that of the first precharging voltage line, and switches such that each signal line has its own one switch serving to connect the signal line to either the first precharging voltage line or the second precharging voltage line; and PA1 operating the switches so that the signal lines are connected to either the first precharging voltage line or the second precharging voltage line thereby precharging the signal lines, wherein the voltages on the first and second precharging voltage lines are periodically inverted. PA1 a first precharging voltage line; PA1 a second precharging voltage line having a voltage different from that of the first precharging voltage line; PA1 switches for selectively connecting the signal lines to either the first precharging voltage line or the second precharging voltage line; and PA1 a switching controller for controlling the on/off operation of the switches. PA1 preparing a first precharging voltage line, PA1 a second precharging voltage line having a voltage different from that of the first precharging voltage line; PA1 first switches provided such that each signal line has its own one first switch for switching the connection/disconnection between the signal line and the first precharging voltage line; PA1 second switches provided such that each signal line has its own one second switch for switching the connection/disconnection between the signal line and the second precharging voltage line; and PA1 a switching controller for controlling the on/off operation of the first and second switches.
The operation of this D/A converter is described below for the specific case where a digital signal of "000001" is input. In this case, the bit D11 of the input signal is "H" (high), and thus an "H"-level signal is held by the latch A11. On the other hand, the bits D12-D16 of the digital input signal are "L" (low), and therefore the latches A12-A16 hold an "L"-level signal. When a latch pulse is input, the signals held by the 1st-stage latches A11-A16 are transferred to the 2nd-stage latches B11-B16 in response to the clock signal CL2 and the inverted clock signal nCL2.
Then the reset signal R on the interconnection line 5006 is raised to "H" thereby turning on analog switches Ta1-Ta6. As a result, the voltage across each conversion capacitor C11-C16 becomes zero, and thus the charge stored in these capacitors goes out. At the same time, an analog switch T3 is turned on so that a charge corresponding to the difference between the voltage of the interconnection line 5003 (Vs) and the voltage of the interconnection line 5004 (GND) is stored in a reference capacitor Cs1. As a result, the reference capacitor Cs1 has a charge Qs given by EQU Qs=Cs1.multidot.Vs (1--1)
Then the reset signal R falls down to "L", and the analog switches Ta1-Ta6 turn off. Furthermore, the set signal S on the interconnection line 5007 is raised to "H". AND operation is performed between the H level of the set signal S and the output level of the respective latches B11-B16. Analog switches Tb1-Tb6 are turned on or off depending on the corresponding results of the AND operation.
In this specific example, the analog switch Tb1 corresponding to the latch B11 is turned on, and, as a result, the conversion capacitor C11 is connected to the reference capacitor Cs1 via the analog switch Tb1. A part of the charge Qs stored in the reference capacitor Cs1 moves into the conversion capacitor C11.
On the other hand, the analog switches Tb2-Tb6 corresponding to the latches B12-B16 are in off-states, and the conversion capacitors C12-C16 are not connected to the reference capacitor Cs1.
As a result of the above operation, the output voltage Vout on the interconnection line 5005 becomes as follows. The charge Qs stored in the reference capacitor Cs1 partially moves into the conversion capacitor C11. After the movement of the charge, the reference capacitor Cs1 has a charge Qs' and the conversion capacitor C11 has a charge Q11' wherein Qs' and Q11' are given by EQU Qs'=Cs1.multidot.Vout (1-2) EQU Q11'=C11.multidot.(Vout-Vo) (1-3)
Here, Qs=Qs'+Q11', thus from equations (1--1) through (1-3), the following equation is obtained. EQU Cs1-Vs=Cs1.multidot.Vout+C11.multidot.(Vout--Vo)
From the above equation, Vout is given as EQU Vout=(Cs1.multidot.Vs+C11.multidot.Vo)/(Cs1+C11)
The above result has been obtained on the assumption that a digital input signal of "000001" is given. If the above discussion is expanded for general digital input signals, then the Vout becomes EQU Vout=(Cs1.multidot.Vs+V11.SIGMA.DiCi)/(Cs1+.SIGMA.DiCi) (1-4)
where the summation .SIGMA. is performed for i=11, 12, 13, 14, 15, and 16, and Di has a value of 1 when the corresponding bits of D11-D16 of the digital signal is at an "H" level while Di has a value of 0 when the corresponding bits of D11-D16 of the digital signal is at an "L" level.
FIG. 75 illustrates the typical conversion characteristic of the conventional D/A converter described above. As can be seen, the analog output signal is a function of the digital input signal wherein the analog output signal varies along a gradually curved line. In other words, the conversion characteristic of the conventional D/A converter is not linear.
The reason for the nonlinearity is that the denominator of equation (1-4) has a term (.SIGMA.DiCi) which varies depending on the values of the bits D11-D16 of the digital input signal, and the variation in this term causes a deviation from the proportional relationship. To avoid the above problem, it is required that the denominator should be a constant.
Furthermore, the conventional D/A converter has discontinuities in its conversion characteristic, which can cause a deviation from a desired output voltage. In FIG. 75, for example, there is a discontinuous reverse change at a point where the digital input signal has a value of "32" in decimal (100000 in binary). That is, the analog output voltage for the input of "32" becomes lower than the output voltage for the input of "31" (011111 in binary). The above discontinuity occurs if the ratio of the conversion capacitance C16 corresponding to the most significant bit to the sum of the conversion capacitances C11-C15 corresponding to the less significant bits has a deviation from an ideal ratio 32:31.
In practice, it is difficult to produce capacitors without introducing any deviation from the ideal values. In particular, in the case of a large capacitance, there is a tendency that the error from the designed value becomes large. For the above reason, the analog output voltage can deviate from the ideal value corresponding to the digital input signal, and the analog output voltage can even decrease with the increase in the digital input signal. This anomalous reduction in the analog output voltage is usually called reversing phenomenon.
(2) Long time required for the output voltage to reach a desired value
It is known in the technology of active matrix display devices, in particular active matrix liquid crystal display device, to precharge signal lines to proper voltages before supplying an image signal onto the signal lines thereby reducing the amount of charge which has to be put or removed onto or from the signal lines by the image signal itself, thus increasing the speed of driving the liquid crystal.
FIGS. 76A and 76B are simplified schematic representations of the operation of precharging signal lines and its effects for the case where a liquid crystal display device of the active matrix type is driven in such a manner that the driving polarity is inverted every horizontal scanning period (or every horizontal line).
In FIG. 76B, "S1" denotes a signal line, and "H1, H2" denote first and second scanning lines, respectively. Reference numerals 6012 and 6014 denote switching devices such as TFTs. Reference numerals 6022 and 6024 denote liquid crystal cells. "C30" denotes a stray capacitance associated with the signal line S1 (that is, the equivalent capacitance of the signal line S1). Furthermore, symbols "-" and "+" on the left side of FIG. 76B indicate that these liquid crystal cells 6022 and 6024 are driven in an inverting fashion. Herein, it is assumed that "black" signals are displayed by the liquid crystal cells 6022 and 6024.
As shown in FIG. 76A, the liquid crystal cell 6022 displays a "black" signal (having a black level voltage B1) during a horizontal scanning period T1. During the following horizontal scanning period T2, the liquid crystal cell 6024 displays a "black" signal (having a black level voltage B2). Although "black" is displayed by both the liquid crystal cells, the signal voltages applied to these cells are opposite in polarity. Therefore, the black level voltages B1 and B2 are at the farthest locations from each other.
If precharging is not performed, the whole stray capacitance C30 associated with the signal line S1 is charged (or discharged) by the image signal itself so that the signal line voltage is changed from the black level voltage B1 to the black level voltage B2 along the curve "R1" in FIG. 76A.
On the other hand, if the signal line is precharged to a voltage with the same polarity as that of the image signal before being driven by the image signal, that is, if the signal line S1 is held at a precharging voltage PV2 before the beginning of the period T2, the image signal is now required only to change the signal line voltage from the precharging voltage PV2 to the black level voltage B1 along the curve "R2" in FIG. 76A. In this case, the image signal line is required to charge the stray capacitance C30 associated with the signal line S1 by only a small amount, and thus high-speed driving of the liquid crystal panel is achieved.
If the resolution of the liquid crystal display panel is increased, it is required to drive the liquid crystal panel at a higher speed and thus it is desirable to precharge each signal line in a shorter time. On the other hand, with the increase in the size of the liquid crystal display panel, the length of each signal line increases and the stray capacitance of the signal line correspondingly increases. This results in an increase in the precharging time.
The above increase in the stray capacitance can make it impossible for the signal line voltage to reach precharging voltage in the given precharging time. The error in the precharging voltage due to the insufficient precharging operation causes an error in the pixel brightness level. Although the signal lines can be precharged in a shorter time period, the reduction in the precharging time results in an increase in power consumption.
In view of the above, the object of the present invention is to provide means for generating a precise voltage in a short time period in a stable fashion.